To cope with the requirements for the development of compact and lightweight electronic machinery and tools, which are likewise greatly improved in their performance, there has rapidly been advanced the investigation and development of smaller, thinner and high density packaged semiconductors. Accordingly, with respect to the packaged structure of such semiconductors, the conventional lead-terminal type ones such as QFP and SOP have been superseded by the area-array type ones such as BGA and LGA, which are highly effective for the realization of thinner and high density packaging. Moreover, it has been a recent trend to positively adopt a stacked-chip multi-layered structure in which a plurality of IC chips are laminated or packaged within a single semiconductor package and in other words, the structure of such a semiconductor package has increasingly been complicated and the packaging density of each semiconductor device has likewise even more rapidly become higher.
In respect of the stacked-chip multi-layered structure, there have been highlighted several problems concerning the moldability thereof due to its complicated structure. This is because, when IC chips are packaged in layers, the difference in height between the portion provided with such chips and that free of any chip on the substrate is considerably increased as compared with that observed for the conventional one chip and accordingly, the semiconductor-sealing material flows through these portions at different speeds. As a result, fine air bubbles are caught in the material at the uppermost narrower portions of the laminated chips at which the flow rate of the material is reduced to thus form un-filled areas (voids). Moreover, the number of gold wires required for the electrical connection of these chips is increased in proportion to the number of chips to be packaged, the use of long-spun gold wires is required and accordingly, problems arise such that such long-spun wires are liable to be deformed by the action of the flowing sealing material (flow resistance thereof) and this in turn results in the contact of a wire with the neighboring one and the formation of a short-circuit.
There have variously been investigated for the solution of these problems, while taking note of the improvement of molds used for molding, and the resins and the fillers used for forming a sealing material for semiconductors. In respect of the improvement of the mold used for molding, there have been proposed, for instance, a technique in which the mold is so designed that it is provided with a groove for exhausting air (air-vent), to thus prevent the formation of any void during the molding operations (Patent Document 1) and a technique in which the mold is so designed that it is provided with a member for controlling the fluidity of a sealing material to thus inhibit the occurrence of any deformation of wires and the formation of any void (Patent Document 2). Moreover, regarding the improvement of the sealing material for semiconductors, there have been proposed, for instance, a method which comprises the steps of reducing the viscosity of a resin to thus precisely control the curing time thereof at the molding temperature (Patent Document 3); a method in which a semiconductor-sealing material comprising a filler and a resin is improved in the property of filling-up narrower portions by reducing the rate of charging of the filler in the resin, lowering the viscosity of the sealing resin and further reducing the particle size of the filler; and a method in which the particle size distribution of a filler to be incorporated into a semiconductor-sealing material is adjusted so as to control the charging (or filling up) property and to simultaneously reduce the viscosity of the sealing material (Patent Document 4). However, these methods have still been insufficient and there has not yet been developed any semiconductor-sealing material which is never accompanied by the formation of voids and the deformation of distributing wires and which can accordingly be used in the sealing of semiconductors having such a stacked-chip multi-layered structure satisfactorily, as well as any ceramic powder used in the sealing material.    Patent Document 1: JP-A-2003-209216;    Patent Document 2: JP-A-2005-310831;    Patent Document 3: JP-A-2006-013382;    Patent Document 4: JP-A-2003-110065.